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Specification
Brand : Juried Engineering
BulletPoint : CD4018BE CD4018 CMOS Presettable Divide-by-N Counter IC Breadboard-Friendly Pack of 5
BulletPoint1 : Synchronous Counting and Loading, Two Count Enable Inputs for n-Bit Cascading, Look-Ahead Carry for High-Speed Counting
BulletPoint2 : Wide Operating Temperature Range . . . -55°C to 125°C, Balanced Propagation Delay and Transition Times, Significant Power Reduction Compared to LSTTL Logic ICs
BulletPoint3 : 2V to 6V Operation, High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
ExternallyAssignedProductIdentifier1 : 0034731416847
ExternallyAssignedProductIdentifier2 : 034731416847
IncludedComponents : Integrated Circuits
ItemName : Juried Engineering CD74HC161E 74HC161High Speed CMOS Logic 4-Bit Binary Counter with Asynchronous Reset DIP-16 Breadboard-Friendly (Pack of 5)
ItemPackageQuantity : 1
ItemTypeKeyword : timing-integrated-circuits
Manufacturer : Juried Engineering
MemorySlotsAvailable : 2
NumberOfDividers : 5
NumberOfItems : 5
PartNumber : M74HC161B1R 4524
ProductDescription : The 74HC161 are presettable synchronous counters that feature look-ahead carry logic for use in high-speed counting applications. The ’HC161 and ’HCT161 are asynchronous reset decade and binary counters, respectively. Counting and parallel presetting are both accomplished synchronously with the negative-to-positive transition of the clock. A low level on the synchronous parallel enable input, SPE, disables counting operation and allows data at the P0 to P3 inputs to be loaded into the counter (provided that the setup and hold requirements for SPE are met). All counters are reset with a low level on the Master Reset input, MR. Two count enables, PE and TE, in each counter are provided for n-bit cascading. In all counters reset action occurs regardless of the level of the SPE, PE and TE inputs (and the clock input, CP, in the HC161). If a decade counter is preset to an illegal state or assumes an illegal state when power is applied, it will return to the normal sequence in one count as shown in state diagram. The look-ahead carry feature simplifies serial cascading of the counters. Both count enable inputs (PE and TE) must be high to count. The TE input is gated with the Q outputs of all four stages so that at the maximum count the terminal count (TC) output goes high for one clock period. This TC pulse is used to enable the next cascaded stage.
ProductSiteLaunchDate : 2018-08-17T07:00:00.000Z
SupplierDeclaredDgHzRegulation : not_applicable
SystemBusStandardSupported : SATA 3
UnitCount : 20
UnspscCode : 32101600